Tools and Benchmarks for Real-Time Systems

Re: The FMTV'16 Challenge

2016-05-20T07:48:53+01:00

Thanks Arne, I think I understand the problem enough to tackle it.

When I analyzed the worst case end-to-end latencies of tasks and chains, too many tasks, 6 out of 21 tasks from my result, violate deadlines even without memory access delay. Chains that have runnables in unschedulable tasks are of course unanalyzable. I'm not sure this unschedulable results have meaning on the challenge, making challenge results not comparable.

Is it OK to leave them unschedulable or should I have to do something like changing some periods to make the whole system schedulable?

Thanks,
Junchul

Hi Junchul,

I would suggest to scale the execution times of the runnables in those tasks, and try to answer the question "What is the maximum execution time for those tasks leading to a schedulable system"?

Arne

Statistics: Posted by arne.hamann — Fri May 20, 2016

Re: The FMTV'16 Challenge

2016-05-20T07:22:41+01:00

Thanks Arne, I think I understand the problem enough to tackle it.

When I analyzed the worst case end-to-end latencies of tasks and chains, too many tasks, 6 out of 21 tasks from my result, violate deadlines even without memory access delay. Chains that have runnables in unschedulable tasks are of course unanalyzable. I'm not sure this unschedulable results have meaning on the challenge, making challenge results not comparable.

Is it OK to leave them unschedulable or should I have to do something like changing some periods to make the whole system schedulable?

Thanks,
Junchul

Statistics: Posted by hinomk2 — Fri May 20, 2016

Re: The FMTV'16 Challenge

2016-05-19T11:51:24+01:00

Hello Arne,

3. Very good question. Right, arbitration is done at the memory, we assume no contention on the crossbar. Actually, we forgot to specify the split in access time between crossbar and memory. So your guess is right: take 8 cycles as transfer delay and 1 cycle for each access.

So 8 cycles of transfer delay is for the round trip, that is, 4 "to" and 4 "back from" the memory, is this right?

Thanks,

Nacho.

Statistics: Posted by Nacho_S — Thu May 19, 2016

Re: The FMTV'16 Challenge

2016-05-19T08:29:51+01:00

Hi, thanks arne for the previous answers.

I have another questions on the memory access model:

1. What happens if preemptive task with higher priority is requested during a resource access of lower priority task? Is the preemptive task blocked until the resource access of lower priority task finishes?

2. Should be a label stored in the local memory when it is fetched from global memory? If my guess is right, total access delay is 9 (to global memory) plus 1 (to local memory). Or is there a temporal storage (such as stack memory area) in a core to store labels for runnable execution?

3. The crossbar has full connectivity. So I guess there is no contention on the crossbar. Then for challenge 2 and 3, the access delay on the memory should be known to compute the arbitration delay, but the access delay in the description seems to include not only memory access delay but also crossbar transfer delay. I guess pure memory access delay is 1 cycle for local/global memory and 8 cycles are crossbar transfer delay, since the cores are symmetric and remote local memory access consists of transfer delay and local memory access delay. Am I right?
For example, suppose a runnable tries to access a label in global memory and there are two access requests in FIFO queue. Then access arbitration delay is 3*9 (9 cycles per each access) if memory access takes 9 cycles. If my guess is right, access arbitration delay is 8(transfer delay) + 3*1(1 cycle per each access).

1. The lower priority finishes its memory access and is only then preempted.

2. There is no local buffering. The data is fetched from global memory and stored into a register. Each access requires thus the full access delay again.

3. Very good question. Right, arbitration is done at the memory, we assume no contention on the crossbar. Actually, we forgot to specify the split in access time between crossbar and memory. So your guess is right: take 8 cycles as transfer delay and 1 cycle for each access.

Statistics: Posted by arne.hamann — Thu May 19, 2016

Re: The FMTV'16 Challenge

2016-05-16T05:11:15+01:00

Hi, thanks arne for the previous answers.

I have another questions on the memory access model:

1. What happens if preemptive task with higher priority is requested during a resource access of lower priority task? Is the preemptive task blocked until the resource access of lower priority task finishes?

2. Should be a label stored in the local memory when it is fetched from global memory? If my guess is right, total access delay is 9 (to global memory) plus 1 (to local memory). Or is there a temporal storage (such as stack memory area) in a core to store labels for runnable execution?

3. The crossbar has full connectivity. So I guess there is no contention on the crossbar. Then for challenge 2 and 3, the access delay on the memory should be known to compute the arbitration delay, but the access delay in the description seems to include not only memory access delay but also crossbar transfer delay. I guess pure memory access delay is 1 cycle for local/global memory and 8 cycles are crossbar transfer delay, since the cores are symmetric and remote local memory access consists of transfer delay and local memory access delay. Am I right?
For example, suppose a runnable tries to access a label in global memory and there are two access requests in FIFO queue. Then access arbitration delay is 3*9 (9 cycles per each access) if memory access takes 9 cycles. If my guess is right, access arbitration delay is 8(transfer delay) + 3*1(1 cycle per each access).

Statistics: Posted by hinomk2 — Mon May 16, 2016

Re: The FMTV'16 Challenge

2016-05-12T16:06:19+01:00

Thanks for the response,

I got some new questions:

- With regard to challenge 1: "ignoring memory accesses" means that the fetching of data in the reading/write phases takes "0" time?
- With regard to challenge 2 when read/write time is not neglected: what happens if a task/runnable/core reads the same label multiple time from GRAM? Does it always pay the same penalty for the access to GRAM, or is there any caching effect? (for example, the data is brought to LRAM the first time, so that successive read/write take less time)

Thanks,

Nacho

Dear Nacho,

here are your answers:
1) yes ;-)
2) There is no caching. Conflicts are arbitrated in a FIFO manner as explained above. The data mapping to LRAM and GRAM is static.

I hope that helps,
Arne

Statistics: Posted by arne.hamann — Thu May 12, 2016

Re: The FMTV'16 Challenge

2016-05-11T17:22:25+01:00

Hi,

I have a question for a given amalthea challenge model.

I started to analyze tasks in model and got a mysterious result.

I added all runnables' upper execution time in Task_10ms, which deadline is 2,000,000 cycles ( 0.01 * 200Mhz), Surprisingly it becomes 2,342,546 cycles in total.

I understood that it means Task_10ms overflows in worst case execution without considering other tasks.

than do I have to analyze it 'mean' execution time? (e.g. lower:452 upper:1782 mean: 979, use 979 to analyze)

or did I analyze model in a wrong way?

I'll wait for your answer :)

Thanks,

Donghyun

Statistics: Posted by kangdongh — Wed May 11, 2016

Re: The FMTV'16 Challenge

2016-05-06T13:58:16+01:00

Thanks for the response,

I got some new questions:

- With regard to challenge 1: "ignoring memory accesses" means that the fetching of data in the reading/write phases takes "0" time?
- With regard to challenge 2 when read/write time is not neglected: what happens if a task/runnable/core reads the same label multiple time from GRAM? Does it always pay the same penalty for the access to GRAM, or is there any caching effect? (for example, the data is brought to LRAM the first time, so that successive read/write take less time)

Thanks,

Nacho

Statistics: Posted by Nacho_S — Fri May 06, 2016

Re: The FMTV'16 Challenge

2016-05-02T16:40:46+01:00

And sorry that I did not reply earlier to the forum post ...that one slipped through :/

Statistics: Posted by arne.hamann — Mon May 02, 2016

Re: The FMTV'16 Challenge

2016-05-02T16:39:57+01:00

Some more questions I received via Email:

1- Are the R/W accesses protected by some kind of semaphore or mutex? If so, what is the shared resource protocol (if any) used to arbitrate the
access to shared resources (SRP, priority ceiling...)?

R/W accesses are arbitrated by the memory in a FIFO manner (no contentions on the interconnect). So accesses to the memory might get blocked by pending accesses from other cores. No locking is performed since the accesses are assumed to be atomic.

2- Is the model of a runnable a Read-Execution-Write (i.e., all read accesses are performed before all the write accesses) or they may be arbitrarily sparse in the code?

Yes, the former.

3- We see many R/W relations through a shared label: why only a very limited subset of these relations belong to an effect chain?

We just defined a few typical effect chains. If you analysis method is in place and general you are free to add more relations ;-)

Statistics: Posted by arne.hamann — Mon May 02, 2016

Re: The FMTV'16 Challenge

2016-04-27T15:52:08+01:00

Hi, we are still working in the challenge and we have some questions to ask you:

- Are the R/W dependencies protected by some kind of semaphore or mutex? If so, what is the shared resource protocol used to arbitrate the access to shared resources (SRP, priority ceiling...)? if any is used.
- Is the model of a runnable a Read-Execution-Write?, that is, is the order of R/W operations like in the XML?. Are all read accesses performed before all the write accesses?
- We see many R/W relations through a shared label, why don't these relations belong to an effect chain?

Best regards

Nacho

Statistics: Posted by Nacho_S — Wed Apr 27, 2016

Re: The FMTV'16 Challenge

2016-04-25T12:10:07+01:00

Hi Junchul,

the unit of runnable execution is instructions. Number of instructions divided by the instructions per cycle (IPC) value from the core (HW element) results to the actual taken time in cpu cycles. In our model, the IPC is 1, so number of instructions equals the number of cycles.

The 0ns delay in the hardware scheduler denotes that there is no scheduling overhead. Every scheduling decision is done in zero time. The 0ms offset at the stimuli means, as you already guessed, that all tasks start the the same time. Yes, all offsets are static.

Best regards,
Simon

Statistics: Posted by Simon Kramer — Mon Apr 25, 2016

Re: The FMTV'16 Challenge

2016-04-25T11:41:53+01:00

Hi,

I have two simple questions.

1) What is the unit of runnable execution lowerbound and upperbound? Is it CPU cycle?

2) There are four schedulers that have 0 ns delay. Also every stimuli has 0 ms offset. I guess it means that all schedulers and stimulis start at the same time (the time system is activated), which is the static offset model. Am I right?

It will be very appreciated if you help me.

Thank you
Junchul

Statistics: Posted by hinomk2 — Mon Apr 25, 2016

Re: The FMTV'16 Challenge

2016-04-21T14:25:29+01:00

Hi all,

I got some new questions:
--
Q:
We are getting interested in the Waters challenge, but we cannot figure out the cooperative scheduling among the tasks that are tagged as such, nor what is the meaning of end-to-end latency in these cases (what is the definition, given that it is a cooperation among periodic tasks sharing variables written asynchronously). Can you help us?

A:
1) Concerning the cooperative scheduling: I think the question is answered above

2) Concerning the meaning of end-to-end latency:

Communication of runnables in the same task: if data is shared among successive runnables inside a runnable there is no additional latency due to the communication. However, if there is a backward communication (i.e. the earlier runnable reads data written by the later runnable) there is one cycle delay until the data is read, i.e. that an effect takes place.

Communication of runnable among tasks: here you need to take over- and under-sampling effects into account. We are generally interest in two different semantics:

Reaction: useful when the first point-in-time that (new) data is read is critical. This is usually of importance, like the name suggests, when system reactivity is required.
Age: useful when the latest point-in-time that (old) data is read is critical. This is usually of importance for control applications

It is sufficient if in a first step you focus first on the reaction sematics
--

I hope the answers help,
Arne

Statistics: Posted by arne.hamann — Thu Apr 21, 2016

Re: The FMTV'16 Challenge

2016-04-21T11:10:54+01:00

Thank you so much, we understand all better :)

Statistics: Posted by Nacho_S — Thu Apr 21, 2016