Tools and Benchmarks for Real-Time Systems

Regular contributions • Re: Extending the Amalthea model to introduce hardware heterogeneity

2018-07-17T18:50:10+01:00

Hello,

please find here my slides -->

PresentationWaters.pdf

Paolo

Statistics: Posted by paolo.burgio — Tue Jul 17, 2018

Regular contributions • Extending the Amalthea model to introduce hardware heterogeneity

2018-07-18T09:59:43+01:00

Title: Extending the Amalthea model to introduce hardware heterogeneity

Authors: Paolo Burgio and Marko Bertogna

Abstract:
In the last years, power-efficient embedded platforms based on heterogeneous multi- and many-core accelerators paved their way in the automotive domain, where size, weight and power (SWaP) are today primary concerns.

Unfortunately, the hardware complexity of such architectures makes "traditional" approaches to timing analysis and real-time scheduling almost unapplicable in the domain.

One of the main reasons is that, these methodologies and tools were originally designed for systems made of few cores, with a simple shared memory sistem, and they lose their effectiveness when applied, e.g., to the complex hierarchical memory system of modern many-cores.

To tackle this problem, in this work we extend a well-known system and execution model, Amalthea, to cope with hardware heterogeneity.

We choose Amalthea because it is widely adopted in the industrial automotive domain, and it is compliant with Autosar.

More specifically, we introduce in the Amalthea specifications the concept of a many-core co-processor/accelerators, which can be either reprogrammable such as a GPU or application specific, such as a NN accelerator, capturing key aspects of the system, such as timing behavior, memory footprint and data transfers between the host and the accelerator.

Our model extensions will support researchers and engineers in designing future real-time automotive systems based on power-efficient embedded architectures.

Statistics: Posted by pagetti — Fri Jun 01, 2018

Regular contributions • Compilation for Real-Time Systems - An Overview of the WCET-Aware C Compiler WCC

2018-05-25T17:41:00+01:00

Titre: Compilation for Real-Time Systems - An Overview of the WCET-Aware C Compiler WCC

Authors:
Dominic Oehlert, Arno Luppold and Heiko Falk

Abstract:
Traditionally, design of embedded hard real-time software and timing analysis are decoupled from each other, leading to complicated design flows involving human interaction. Furthermore, traditional compilers optimize for average-case performance so that no tool support exists supporting the designer to systematically reduce Worst-Case Execution Times in case that deadlines are missed.

The WCET-aware C Compiler WCC improves this situation by tightly integrating timing analyses (both static WCET analyses as well as schedulability analyses) into the compilation and optimization flow. Furthermore, the compiler features dedicated real-time aware optimizations and exploits detailed architectural knowledge so that schedulable code meeting deadlines can be generated automatically, even for multi-task or multi-core systems.

WATERS_WCC.pdf

Statistics: Posted by pagetti — Fri May 25, 2018

Regular contributions • Bosch WATERS Challenges Reloaded: Moving from Classical to High Performance Real-time Systems

2018-05-24T12:31:40+01:00

Title: Bosch WATERS Challenges Reloaded: Moving from Classical to High Performance Real-time Systems

Authors: Arne Hamann

Abstract:
he Bosch WATERS challenges in 2016 and 2017 addressed problems arising in "classical" real-time systems composed of mostly periodic tasks in the domain of engine management executed on µC platforms. In this talk will give a retrospective of the challenges and the impact in the real-time community so far. Meanwhile, established engineering practices in the embedded real-time industry are put to the test by a new class of systems: ADAS applications executing on high-performance platforms comprising µPs and accelerators such as GPUs. Such systems require novel analytic approaches as well as mechanisms constructively controlling contention effects on the multi-level memory hierarchy to ensure timing predictability. Motivated by the success of the 2016 & 2017 challenges the talk will announce a new challenge for 2019 with focus on ADAS applications executed on high performance platforms.

Statistics: Posted by pagetti — Thu May 24, 2018

Regular contributions • RTProb - Real Time Probabilistic Tool for Probabilistic Schedulability Analysis using Markov Chain

2018-05-23T14:01:42+01:00

Title: RTProb - Real Time Probabilistic Tool for Probabilistic Schedulability Analysis using Markov Chain

Authors: Jasdeep Singh, Luca Santinelli, David Doose, Julien Brunel and Guillaume Infantes

Abstract: This paper presents a probabilistic schedulability analysis tool for probabilistic Real-Time Systems (pRTS). By pRTS we mean a real-time system in which at least one of its parameter is defined using a probability distribution; in our case this parameter is the task Worst Case Execution Time (WCET) which is the probabilistic, called probabilistic WCET (pWCET). The tool implements a formalism which is based on formal methods for modelling and analysis of pRTSs. It uses pWCETs to construct Continuous Time Markov Chain models, one per task job. For each job, the CTMC describes the job execution by taking into account all the interferences (probabilistic delays) that might exist. The tool also interfaces with model checkers for checking the models built. The results of the analysis as given by the tool are the probability of deadline miss and the response time curves for each task and for each job of the tasks.

Tool_Paper.pdf

Statistics: Posted by pagetti — Wed May 23, 2018

Regular contributions • Modeling Accesses to Shared Memories in Multi-Processor Systems-on-Chip (MPSoCs)

2018-05-23T13:59:28+01:00

Title: Modeling Accesses to Shared Memories in Multi-Processor Systems-on-Chip (MPSoCs)

Authors: Adam Kostrzewa, Selma Saidi and Rolf Ernst

Abstract:
Multi-Processor Systems-on-Chip (MPSoCs) enable high performance through integration and concurrent execution of previously separated applications and functions. However, due to an extensive sharing of hardware components, the prediction of the timing behavior in such systems becomes complicated. Even in setups with static task-to-processor mapping, the real-time analysis of accesses to shared memories is non-trivial as it includes the acquisition of several system resources, e.g., interconnect and controllers, and a broad spectrum of possible interference.
In this talk, we discuss how to apply the Compositional Performance Analysis framework to model these new dependencies and bound the worst-case latencies in a shared memory system efficiently. We show that careful management of data storage and transfers in the MPSoC is critical for achieving the performance and safety. Furthermore, we present how effects of locality of accesses and their granularity influence the response time and introduce dynamic hardware effects which must be covered by the analysis.

waters_2018_akostrzewa_ver4.pdf

modeling-accesses-shared.pdf

Statistics: Posted by pagetti — Wed May 23, 2018

Regular contributions • Applying formal methods to the configuration and verification of Trampoline RTOS

2018-05-23T13:51:49+01:00

Title: Applying formal methods to the configuration and verification of Trampoline RTOS

Authors: Jean-Luc Béchennec, Olivier H. Roux and Toussaint Tigori

Abstract: The low-level software of small embedded systems and especially the operating system must be configured and adapted to a given application. This specialization has several goals such as reducing memory usage, improving performance or removing dead code. However, traditional configuration methods do not guarantee that the component configured for the application continues to meet the specifications and it is not possible to use a test suite for the configured component since the test suite itself requires different configurations.

One possibility is to formally model the component at its source code level. Once completed by an application model, the parts of the component model that are not reachable correspond to dead code and can be removed. In this way a configured model is extracted. The verification of the component, whether it is configured or not, can be done by means of observers. Finally, since the modeling is done at the source code level, the configured component code can be generated.

Statistics: Posted by pagetti — Wed May 23, 2018

Regular contributions • Challenges in partitioned systems based on hypervisor: XtratuM case

2018-05-23T13:51:15+01:00

Title: Challenges in partitioned systems based on hypervisor: XtratuM case

Authors: Alfons Crespo

Abstract:
The increase in processor power and the availability of multi-core systems have extended the possibilities of integrating different applications into the same hardware. Although the concept of Integrated Modular Avionics (IMA) was developed for single-core platforms, the increasing importance of (heterogeneous) multi-core platforms provides additional relevant value to this approach. In this line, researchers and industry are making significant efforts to analyse and exploit the capabilities of these platforms taking into account their advantages and limitations. Greater performance increased computing power, and stricter cost-containment is counteracted by the difficulty of computing exact execution time due to the effects of shared resources on code execution. Other sectors, such as space, railway, automobile, industry & IoT, etc., are also using partitioned systems.

Partitioned systems based on hypervisor allow guaranteeing the fault isolation by enforcing the temporal and spatial partitioning of the system and increasing the security and confidentiality of the applications.
The XtratuM hypervisor is a bare-metal hypervisor for embedded real-time systems that have been used in several EU projects and is currently being used on several space missions. Initially developed for LEON processors, it has been adapted to other platforms such as ARM Cortex R4/R5, A9 and PowerPC.
XtratuM has incorporated technologies such as MMU, multi-core, heterogeneous platforms, networked systems, application execution control, hardware virtualization support, etc., which has allowed it to be a reference hypervisor. Several applications with different levels of criticality and using different resources (guestOS) can coexist managed by the hypervisor.

This presentation will detail the evolution of Xtratum, the application fields and scenarios and the main issues to address the new challenges.

Statistics: Posted by pagetti — Wed May 23, 2018